BM1002 COMPUTER ARCHITECTURE 3 0 0 100
To discuss the basic structure of a digital computer and to study in detail the organization of the Control unit, the Arithmetic and Logical unit, the Memory unit and the I/O unit.
• To have a thorough understanding of the basic structure and operation of a digital computer.
• To discuss in detail the operation of the arithmetic unit including the algorithms &
implementation of fixed-point and floating-point addition, subtraction, multiplication & division.
• To study in detail the different types of control and the concept of pipelining.
• To study the hierarchical memory system including cache memories and virtual memory.
• To study the different ways of communicating with I/O devices and standard I/O interfaces.
1. INTRODUCTION 9
Computing and Computers, evolution of computers, VLSI era, system design- register level, processor level, CPU organization, Data representation, fixed – point numbers, floating point numbers, instruction formats, instruction types.
2. DATA PATH DESIGN 9
Fixed point arithmetic, addition, subtraction, multiplication and division, combinational and sequential ALUs, carry look ahead adder, Robertson algorithm, booth’s algorithm, non-restoring division algorithm, floating point arithmetic, coprocessor, pipeline processing, pipeline design, modified booth’s algorithm
3. CONTROL DESIGN 9
Hardwired Control, micro programmed control, Multiplier control unit, CPU control unit, Pipeline control, instruction pipelines, pipeline performance, super scaling processing, Nano programming.
4. MEMORY ORGANIZATION 9
Random access memories, serial access memories, RAM interfaces, magnetic surface recording, optical memories, multilevel memories, Cache & virtual memory, memory allocation, Associative memory.
5. SYSTEM ORGANIZATION 9
Communication methods, buses, bus control, bus interfacing, bus arbitration, IO and system control, IO interface circuits, DMA and interrupts, vectored interrupts, PCI interrupts, pipeline interrupts, IOP organization, operation systems, multiprocessors, fault tolerance.
TOTAL : 45
1. Morris Mano, “Computer System Architecture”, Prentice-Hall of India, 2000.
2. John P.Hayes, ‘Computer architecture and organisation’, Tata McGraw-Hill, Third edition, 1998
1. V.Carl Hamacher, Zvonko G. Varanesic and Safat G. Zaky, “ Computer Organisation” IV edition, McGraw-Hill Inc, 1996.
2. H.S. Stone, “High Performance computer architecture”, Addison Wesley, Third Edition, 1993.
3. K.Hwang, “Advanced computer architecture”, Tata McGraw-Hill, 1993.
4. J.Vaideeswaran, “ Computer architecture”, New Age International, 1999.
5. G.Kane & J.Heinrich, “MIPS RISC Architecture”, Englewood cliffs, New Jersey, Prentice Hall, 1992.