EC1404 VLSI Lab Syllabus

EC1404 VLSI LABORATORY 0 0 3 100

1. Study of Simulation using tools
2. Study of Synthesis tools
3. Place and Root and Back annotation for FPGAs
4. Study of development tool for FPGAs for schematic entry and verilog
5. Design of traffic light controller using verilog and above tools

6. Design and simulation of pipelined serial and parallel adder to add/ subract 8 number of size, 12 bits each in 2's complement
7. Design and simulation of back annotated verilog files for multiplying two signed, 8 bit numbers in 2's complement. Design must be pipelined and completely RTL compliant
8. Study of FPGA board (HTTP://www.xess.com) and testing on board LEDs and switches using verilog codes
9. Testing the traffic controller design developed in SI. NO.5 on the FPGA board
10. Design a Realtime Clock (2 digits, 7 segments LED displays each for HRS., MTS, and SECS.) and demonstrate its working on the FPGA board. An expansion card is required for the displays.
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